module AD_1BY1 (
	iLDATA[7:0],
	iRDATA[7:0],
	AD[7:0]);
	
input	[7:0] 	iLDATA, iRDATA; // Input data
output 	[7:0] 	AD; // Sum of absolute differences

//compute absolute differences
assign AD = (iLDATA[7:0] < iRDATA[7:0]) ? (iRDATA[7:0] - iLDATA[7:0]) : (iLDATA[7:0] - iRDATA[7:0]);

endmodule